1. Field of the Invention
The present invention relates to a multilayer circuit board and the method for manufacturing the same, and more particularly, to a substrate with a multilayer plated through hole and the method for forming the multilayer plated through hole.
2. Description of the Related Art
In general, multilayer circuit boards are frequently used in most electronic devices as media for signal transmission, power supply and grounding. As the electronic devices get complex and have more function, the number of trace layers of the multilayer circuit boards and longitudinal electrical connections between the trace layers are becoming greater. Accordingly, it is required to form much more plated through holes (PTHs) as electrical channels between these trace layers.
The Taiwan Patent Publication Number 589729, entitled “SUBSTRATE WITH VIA HOLE HAVING SHIELDING FUNCTION AND FORMING THE SAME”, discloses a substrate with via holes. The inner wall of the via hole is first formed with a barrel-shaped shielding layer and then covered by a dielectric layer. A signal channel is deployed in the via hole. The via hole is formed by first filling up the barrel-shaped shielding layer with a dielectric material and then drilling the dielectric material to form a hole. A signal channel is subsequently deployed in the hole. However, the way to form a via hole by drilling cannot precisely control the thickness of the resulting dielectric layer. This will cause the separation of the signal channel from the shielding layer to be non-uniform and even a short circuit. The way of forming a via hole by drilling is inappropriate to a substrate with a multilayer plated through hole.
The Taiwan Patent Number 1242783, entitled “CUT VIA STRUCTURE FOR AND MANUFACTURING METHOD OF CONNECTING SEPARATE CONDUCTORS”, discloses a cut via structure. The cut via structure includes at least two separate conductors formed with a central hollow or filling structure. The gap between the separate conductors is formed in a vertically-cut or slanted-cut direction with respect to the cut via structure. In brief, it is to divide a via hole into two or more parts, and each of which is connected to at least one of top traces and bottom traces. However, when at the period of division of the via hole or even application to an end-product, such separation of one conductor from the other will result in a degradation of the via structure. A temperature change experienced by the substrate is likely to cause the via structure to be broken. The conventional coaxially paired via structure disclosed in above-identified patent has the disadvantage of high impedance and producing an induction. This is because the way of forming the dielectric layer is to fill up the via hole with a dielectric material and then drill the via hole. A signal channel is subsequently deployed in the via hole. This will cause the thickness of the resulting dielectric layer to be uneven and consequently result in the above-mentioned disadvantage.